module par_ser(rst,clk,dout,din,en);
input rst,clk,en;
input [7:0] din;
output dout;
reg [7:0] buffer;
always @(posedge clk or posedge en)
begin
	if(!rst)   //di
	buffer=1'b0;
	else if(en)
	         buffer<=din;
	     else
	       buffer<=buffer<<1;
end
assign dout=buffer[7];
endmodule	